1. Field of the Invention
The present invention relates to the field of memories, and more specifically to DRAMs.
2. Discussion of the Related Art
Typically, a DRAM includes a memory plane formed with an array of elementary memory cells, a row decoder and a column decoder. Each memory cell is located at the intersection of a row (word line) and of a column (bit line).
The column decoder conventionally includes an input for data writing and an output for data reading. The column decoder is controlled by a column address strobe (CAS), a column address signal (CAD), and a read/write signal generally called R/W.
The row decoder is controlled by a row address strobe (RAS), a row address signal (RAD), and signals used to refresh the memory.
Conventionally still, amplifiers providing access to the memory plane (SENSE AMP) will be located on each bit line, between the memory plane and the column decoder. They enable isolating the memory cells and allow their reading, writing or refreshment.
DRAMs have the advantage of having a large storage density, but, in addition to the fact that a refreshment of the memory cells is necessary, they have the disadvantage of being slow in terms of access time.
As an example, FIG. 1 shows a timing diagram of signal RAS for a conventional DRAM, illustrating the time required to process an access request. It is assumed that at a time t0, the DRAM receives an access request, signal RAS already being at its preload level. The desired data will be accessible at the output of the memory plane at a time t1 only. Then, a time t2 must be awaited for all the desired words of a data row (or word page) to be read at the output of the sense amplifiers (case of a reading) or written into the memory (case of a writing). Only then can signal RAS return to its preload level, where it will have to stay at least during preload time tPR (typically 3 clock cycles) before the memory is available for a new access. Thus, the time between two successive accesses to the memory is t3-t0.
To improve the access time, it has been devised to add to the DRAM a cache memory enabling writing the data of the main memory as soon as they are available, that is, in the preceding example, at time t1, to reset the main memory to preload as soon as the data have been loaded in the cache memory, the data now stored in the cache memory being readable at the user""s will. As illustrated in FIG. 2, the main memory is available again for a new request at time txe2x80x21, corresponding to time t1 plus preload time tPR, but it must in practice be awaited until the data of the cache memory have been read before being able to have access again to the memory plane. In the example of FIG. 2, a burst of 5 data is shown, and the memory will only be usable at time t2. In terms of access time, the time spared in the example is preload time tPR, since signal RAS no longer needs be set to preload at a time t2. If, however, the data burst has a duration shorter than the preload time (typically less than three data), the memory becomes accessible at time txe2x80x21 and, as compared to conventional memories, the time gain is that of the data burst.
It can thus be seen that the DRAM structure with a cache memory improves the time of access to the DRAM, but not significantly. Further, the improvement only concerns the reading, and not the writing. Moreover, in such arrangements, the cache memory often has a limited capacity, which all the more delays the processing of long bursts or of bursts including words distant by a line.
In French patent application xe2x80x9cDRAM à structure rapidexe2x80x9d filed on Mar. 26, 1998 under number 98/04008, the applicant provides a DRAM including two cache registers for storing a current page and another page of the memory, such as the next memory page, to accelerate the processing of requests. This application above all relates to the circuits forming the memory, and to its refreshment. It does not describe all possibilities of use of the memory and of its cache registers. Neither does it describe a memory controller for controlling the memory.
An object of the present invention is to provide a method for controlling a DRAM including two cache registers.
Another object of the present invention is to provide a memory controller enabling controlling a DRAM including two cache registers.
To achieve these objects as well as others, the present invention provides a method for controlling a dynamic random access memory (DRAM) including a memory plane formed of an array of memory cells and at least two cache registers. The method includes the steps of:
receiving a request for access to the memory which is part of a sequence of synchronous requests of a clock, said request comprising at least a page address, a column address, a write or read order and, in case of a write request, data to be written,
comparing the page address of the current request with the page address of the preceding request,
storing, in the case where the page address of the current request is different from that of the preceding request, the new page in one non-used of the two cache registers, preferably that which has not been used last,
storing in a storage element the column address and, if present, the data to be written of the current request, to make them available when the page of the current request is itself available in one of the cache registers, and
using an output of said storage element to have access, from the considered cache register, to the desired words of the current request page.
According to an embodiment of the present invention, said storage element includes a first register, the content of the first register being transferred to a second register, and the second register is formed of a set of sub-registers forming a shift register, the content of the second register advancing upon each clock pulse towards an output of said second register to delay the column address and the possible data to be written by a duration equal to the time required to load a page, from the memory plane, into one of the cache registers.
According to an embodiment of the present invention, in the case of a reading, the data present at the output of said storage element enable direct access, in the cache register used, to the words located by their column address.
According to an embodiment of the present invention, in the case of a writing, the data present at the output of said storage element enables loading the words to be written into said cache register, the page thus modified remaining stored in said cache register, waiting to be written back upon a next access to the memory plane.
According to an embodiment of the present invention, if no access to the memory plane is required for a reading or a writing, the refreshment of a row of the dynamic memory is performed, the cache registers, isolated from the memory plane, being available for use during the refreshment.
According to an embodiment of the present invention, when the page of the current request is a new page and it cannot be loaded into one of said cache registers, the current request is stored in appropriate means until the loading can occur.
The present invention also provides a memory controller for controlling a DRAM including a memory plane formed with an array of memory cells and at least two cache registers, the controller receiving as an input a request for access to the memory, said request being part of a sequence of synchronous requests of a clock and comprising at least a page address, a column address, a write or read order and, in case of a write request, data to be written. The controller includes a control block adapted to managing the controller operation and to providing signals of access to the memory plane. The controller further includes:
a comparator associated with a memory element for comparing the page address of the current request with the page address of the preceding request,
a storage element for storing the column address and, if present, the data to be written of the current request, and for delaying these data by the time required to load a page into one of the cache registers from the memory plane, so that the column address and the possible associated data of the current request are made available when the content of the page of the current request is itself available in one of the cache registers.
According to an embodiment of the present invention, the storage element includes:
a first register for storing the column address and, if present, the data to be written of the current request, and
a second register, receiving as an input the output of said first register and providing as an output control signals of the cache registers, said second register being formed of a set of n sub-registers forming a shift register, the number of the sub-registers being chosen to delay the data at the output of the second register by the time required to load a page into one of the cache registers from the memory plane, so that the column address and the possible associated data of the current request are made available when the content of the page of the current request is itself available in one of the cache registers.
According to an embodiment of the present invention, the number of sub-registers depends on the clock frequency and on the time of access to the DRAM, this number being equal to 4 when the clock frequency is 200 MHz and the time of access to the DRAM is 20 nanoseconds.
According to an embodiment of the present invention, the controller further includes an additional memory, for example of FIFO type, for receiving the requests as an input, said memory being adapted to queuing the requests.